source: Intel DPDK Patches/hardware_timestamp.patch @ 82facc5

4.0.1-hotfixescachetimestampsdevelopdpdk-ndagetsilivegetfragoffhelplibtrace4ndag_formatpfringrc-4.0.1rc-4.0.2rc-4.0.3rc-4.0.4ringdecrementfixringperformanceringtimestampfixes
Last change on this file since 82facc5 was c04929c, checked in by Richard Sanger <rjs51@…>, 9 years ago

Added the new live trace format Intel DPDK - See the wiki for more documentation
  • Property mode set to 100644
File size: 1.1 KB

  • lib/librte_pmd_e1000/igb_rxtx.c 

    diff -ur ./DPDKORG/lib/librte_pmd_e1000/igb_rxtx.c ./DPDK/lib/librte_pmd_e1000/igb_rxtx.c
    old new  
    16561656                if (rxq->drop_en)
    16571657                        srrctl |= E1000_SRRCTL_DROP_EN;
    16581658
     1659                /* Place timestamps at the start of the receive buffer */
     1660                srrctl |= E1000_SRRCTL_TIMESTAMP;
     1661
    16591662                E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
    16601663
    16611664                /* Enable this RX queue. */
    … …  
    17511754        /* Enable Receives. */
    17521755        E1000_WRITE_REG(hw, E1000_RCTL, rctl);
    17531756
     1757        /* Timestamp every rx packet */
     1758        rctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
     1759        rctl &= ~(E1000_TSYNCRXCTL_TYPE_MASK);
     1760        rctl |= E1000_TSYNCRXCTL_ENABLED;
     1761        rctl |= E1000_TSYNCRXCTL_TYPE_ALL;
     1762        E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, rctl);
     1763
     1764        rctl = 0;
     1765        E1000_WRITE_REG(hw, E1000_TSYNCRXCFG, rctl);
     1766        /* Start the clock timestamping */
     1767        E1000_WRITE_REG(hw, E1000_TSAUXC, 0x0);
     1768        E1000_WRITE_FLUSH(hw);
    17541769        /*
    17551770         * Setup the HW Rx Head and Tail Descriptor Pointers.
    17561771         * This needs to be done after enable.
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