source: Intel DPDK Patches/hardware_timestamp.patch

4.0.1-hotfixescachetimestampsdevelopdpdk-ndagetsilivegetfragoffhelplibtrace4ndag_formatpfringrc-4.0.1rc-4.0.2rc-4.0.3rc-4.0.4ringdecrementfixringperformanceringtimestampfixes
Last change on this file was c04929c, checked in by Richard Sanger <rjs51@…>, 7 years ago

Added the new live trace format Intel DPDK - See the wiki for more documentation

  • Property mode set to 100644
File size: 1.1 KB
RevLine 
[c04929c]1diff -ur ./DPDKORG/lib/librte_pmd_e1000/igb_rxtx.c ./DPDK/lib/librte_pmd_e1000/igb_rxtx.c
2--- ./DPDKORG/lib/librte_pmd_e1000/igb_rxtx.c   2013-06-24 10:21:14.000000000 +1200
3+++ ./DPDK/lib/librte_pmd_e1000/igb_rxtx.c      2013-07-12 16:59:57.000000000 +1200
4@@ -1656,6 +1656,9 @@
5                if (rxq->drop_en)
6                        srrctl |= E1000_SRRCTL_DROP_EN;
7 
8+               /* Place timestamps at the start of the receive buffer */
9+               srrctl |= E1000_SRRCTL_TIMESTAMP;
10+
11                E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
12 
13                /* Enable this RX queue. */
14@@ -1751,6 +1754,18 @@
15        /* Enable Receives. */
16        E1000_WRITE_REG(hw, E1000_RCTL, rctl);
17 
18+       /* Timestamp every rx packet */
19+       rctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
20+       rctl &= ~(E1000_TSYNCRXCTL_TYPE_MASK);
21+       rctl |= E1000_TSYNCRXCTL_ENABLED;
22+       rctl |= E1000_TSYNCRXCTL_TYPE_ALL;
23+       E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, rctl);
24+
25+       rctl = 0;
26+       E1000_WRITE_REG(hw, E1000_TSYNCRXCFG, rctl);
27+       /* Start the clock timestamping */
28+       E1000_WRITE_REG(hw, E1000_TSAUXC, 0x0);
29+       E1000_WRITE_FLUSH(hw);
30        /*
31         * Setup the HW Rx Head and Tail Descriptor Pointers.
32         * This needs to be done after enable.
33
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