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Mark Will's blog

16

Sep

2013

I've spent this week writing my report, which from the current progress is going to be huge. There are still a few things I need to finish in order to get more results for the report, like the neon implementation but I hope to work on those next week.

12

Aug

2013

I've nearly got the FFT working in hardware with a device driver and system call for linux so I can just swap out the fft function for the hardware version in my code for performance testing. It has been a mission getting this far with so many little issues occurring which take ages to debug and fix.

10

Jul

2013

I've managed to read and write to DDR3 from the FPGA on the zedboard which was a mission. There's still an issue with writing but once thats fixed, I can test burst read and burst write, then connect up a FFT core.

01

Jul

2013

This week we've realised I need another license to get support/access to a beta feature in Vivado HLS which allows it to infer a FFT core directly from the C code. Hopefully this doesn't take to long to sort out. I'm still trying to figure out if there is an easy way for Vivado HLS to create a DDR memory interface with support for multiple stages in the pipeline accessing it. However currently it just creates multiple external connections which need to be handled by an interconnect.

25

Jun

2013

I've finished the C code now and I'm currently trying to use the Xilinx Vivado tool to convert it to VHDL. This is proving to be harder than I thought however I'm making good progress. At the moment I'll only running it on part of the code but once I'm comfortable with the tool I'll be able to convert my whole program. Hopefully only the FFT function will be a problem.

10

Jun

2013

This past week I've been finishing off all my other papers for semester A. Now I can focus on honours for the next 4 weeks.

28

May

2013

This week I've spent most of my time doing my report, plus starting to
rewrite more of the code to make it faster. Also being working on my 560
assignment, building a deep packet inspector in a FPGA which is going
well, hopefully have it running by next week.

20

May

2013

This week I've re-writing the code so I can start to optimise it. Mainly converting the use of a mix of 1D and 2D arrays to just using 1D arrays. It took a while to fix all the bugs this caused. I've also started writing my report.

13

May

2013

This week I've spent most of the time doing other assignments, one of which is a deep packet inspector in a FPGA. But I have managed to get the code starting to handle x y translations and early results are looking promising. Over the next few weeks I'll be writing the mid term report so I'm not sure how much time I'll get on the actually project.

06

May

2013

I've managed to get my program to take in a video in a number of formats and convert them to a usage format and process them frame by frame. Sadly that's all I did since I was having problems getting the library to work properly. But now I can start looking at the output and stabilizing X and Y movements.